Mission Possible
Development of Project-based Teaching Modules for Communications, Networking, and Air- and Space-born Data and Signal Processing Using Reconfigurable and Programmable Platforms
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Mission PossibleDevelopment of Project-based Teaching Modules for Communications, Networking, and Air- and Space-born Data and Signal Processing Using Reconfigurable and Programmable Platforms |
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PI: Dr. Emma E. Regentova
Co-PIs: V. Muthukumar
Electrical and Computer Engineering Department
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NASA planetary and earth sciences missions assume high-speed and low-power on-board computations related to control, navigation, data collection and communication algorithms. Reconfigurable Field Programmable Gate Arrays (FPGAs) and programmable platforms such as embedded digital signal processors (DSP) provide flexible hardware and software co-design architectures to meet the on-board data processing challenges of these missions. FPGA and embedded DSP processors are engines for meeting execution time and power requirements with the balance of the payload. On-board mission data are generated by high data rate scientific instruments. Their pre-processing, enhancement, quality assessment, analysis and transmission constitute major goals of any science mission. Acquired on the board data are bandwidth and memory demand. The future missions' modern instruments are expected to reach approximately 1-5 Terabytes per day according to internal studies at NASA's Jet Propulsion Laboratory (JPL). The goal of this project is to engage students to the development of source and channel coding circuits and analyze them based on the component use, power consumption, memory usage, time, and haracterize them for on-board satellite/spaceship implementation. This is expected to increase students' awareness of techology needs and prepare them for the career development with NASA. |
Student participants and projects developed in CPE 403, CPE 405 and CPE 409
| Reiner Dizon, CPE 405, Honors thesis | Implementation of CCSDS 121.0-B-1 lossless image compression standard:, Presentation |
| Eilat Avidan, CPE 405, Final Project | Circuit design for LZSS lossless coding, Report, Presentation |
| Angel Solis, CPE 405, Final Project | Software implementation and testing of CRC-16, Report |
| Damian Cimneros, CPE 405, Final Project | Implementation and testing of SHA-1, Report |
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Trace Stewart, CPE 405, Final Project |
Using NIOS II Altera DE2i-150 in embedded design, Tutorial |
| Emmanuel R. Lopez, CPE 405, Final Project | Circuit for bidirectional reversible variable length (ref) decoding, Presentation |
| Reiner Dizon, CPE 409, HW | Circuits for image resizing, Sobel operator, Image crossfading, HW |
| Reiner Dizon, CPE 409, Final Project | Circuit for Canny edge detector. Demo. |
| Trace Stewart, CPE 409, Midterm Project | Circuit for motion/direction detection in live video. Demo |
| Jacob Sherman, CPE 409, Midterm Project | Circuit for implementing 5x5 median filter on live video. Verilog modules. |
| Reiner Dizon, CPE 403, Final Project | RPLIDAR 360 Laser, Demo |
| Joseph Kim, CPE 403, Final Project | Robot Turret, Demo |
| Reiner Dizon, Angel Solis, CPE 405, Project | Circuit for Huffman Encoding: Sorting (ref), calculating lengths, canoncal tree construction. |
| Junho Bae, CPE 40, Final Project | Stereo Vision and the depth map with BBB. Demo |
| Lyuben Hristov, CPE 403, Final proect |
Hydroponics Monitoring System, Demo |
| Reiner Dizon, CPE 405, Final Project | CRC 16 CCIT, Report |
