CPE100-1002 Logic Design I

Spring 2014

Class meets: MW 1:00-2:15pm in TBE B-174

Instructor: Dr. Yingtao Jiang

Office: SEB 4218

Phone: (702) 895-2533

Fax: (702) 895-4075

Office Hours: MW 2:30pm -5:30pm

Email: yingtao.jiang@unlv.edu

Course Website: http://www.ee.unlv.edu/~yingtao/2014_Spring/CpE100/cpe100_syllabus_2014Spring.htm

Course Description

This course provides an introduction to digital systems, digital design principles, and computer systems. 3 credit hours.

Course Objectives

To gain the knowledge on

· number systems and binary arithmetic, basics of switching algebra, simplification and minimization methods for Boolean functions

· basic gates and simple integrated circuits that can be used for combinational network design

· different types of flip-flops, basics of sequential network design

Course Prerequisites

MATH 127 or MATH 128

Textbook

Fundamentals of Logic Design, 7^th edition

Charles H. Roth and Larry L. Kinney

Supplementary Materials

Class handouts & notes

Homework assignments and solutions (click)

Lecture Notes	Posting Date
Unit 1	01/21/2014
Unit 2	01/25/2014
Unit 3	01/25/2014
Unit 4	01/25/2014
Unit 5	02/01/2014
Unit 6	02/09/2014
Unit 7	02/13/2014
Unit 8	02/18/2014
Unit 9	02/23/2014
Unit 11	03/04/2014
Unit 12	03/20/2014

Topics

Unit 1	Introduction Analog and digital systems and their difference Binary number systems Number Systems and Conversion Conversion between different number systems Binary arithmetic Representation of negative numbers Binary codes (BCD, gray code, etc.)
Units 2 & 3	Boolean Algebra Boolean expressions and truth tables Basic theorems Commutative, associative, and distributive laws Simplification theorems and methods DeMorgan’s laws Exclusive-OR and equivalence operations The consensus theorem Algebraic simplification and switching expressions Proving validity of an equation
Unit 4	Application of Boolean Algebra/Minterm and Maxterm Expansions Definitions of Minterm and maxterm General minterm and maxterm expansions Design of binary adders and subtractors
Unit 5	Karnaugh Maps (K-Maps) Minimum forms of switching functions Two, three, four, and five-variables K-maps Determination of minimum expressions
Unit 6	Quine-McCluskey Method Determination of Prime Implicants The Prime Implicant Chart
Unit 7	Multi-Level Gate Circuits/NAND and NOR Gates Multi-level gate circuits NAND and NOR gates Design of two-level circuits and multi-level circuits using NAND and NOR gates Design of multi-level, multi-output circuits
Unit 8	Combinational Circuit Design and Simulation Using Gates Design of circuits with limited gate fan-in Gate delays and timing diagrams Hazards in combinational logic Simulation and testing of logic circuits
Unit 9	Multiplexers, Decoders, and Programmable Logic Devices Three-state buffers Decoders and encoders Read-only memories Programmable logic devices Complex programmable logic devices Field programmable gate arrays
Unit 11	Latches and Flip-Flops Set-reset latch Gated D Latch Edge-triggered D flip-flop S-R, J-K, and T flip-flops Flip-flops with additional inputs
Unit 12	Registers and Counters Registers and register transfers Shift registers Design of binary counters Counters for other sequences Counter design using S-R and J-K flip-flops

Evaluation

1. There will be a few quizzes, one midterm exam, and one comprehensive final exam. Quizzes and the exams are close book and close notes. Questions are designed to be answered with simple mathematics. The use of calculators is not allowed.

2. There will be a number of homework assignments. In general, homework will be due one week from the date it is assigned, returned and (solution) posted in one week from the due date. Late assignments will not be accepted. Staple your paper sheets together. Loose papers will not be accepted. A student who fails to turn in 80% of the homework assignments will not be allowed to sit in the final exam.

3. Distribution of final grade:

Quizzes 10%
Midterm Exam 30%
Final Exam 60%

Attendance Policy

Attendance is required. You are responsible for all class work missed, regardless of the reason for the absence(s). No makeup exams will be given. It is your responsibility to check the course website for all activities going on with this course.

Academic Dishonesty

Academic dishonesty includes, but is not limited to, activities such as cheating and plagiarism. Any work turned in for individual credit must be entirely the work of the student submitting the work. You may share ideas but submitting identical assignments (for example) will be considered cheating. For assignments, access to notes, the course textbooks, books and other publications is allowed. All work that is not your own, MUST be properly cited. This includes any material found on the Internet. Any person caught cheating will be given an ‘F’ grade for the course and reported to appropriate university officials.

ADA statement
If you have a documented disability that may require assistance, you will need to contact the Disability Resource Center (DRC) for coordination in your academic accommodations. The DRC is located in the Reynolds Student Service Complex in room 137. Call at 895-0866 or TDD 895-0652, visit the DRC website at: http://www.unlv.edu/studentlife/disability/.