University of Nevada, Las Vegas

Department of Electrical and   Computer Engineering

 

 

EE 427/ECG 615 Introduction to VLSI System Design

Fall 2010

 

Instructor:                            Dr. Y. Jiang

                                                SEB 4218

                                                895-2533

                                                yingtao@egr.unlv.edu

 

Office Hours:                       Mondays and Wednesdays 1:30 pm – 2:30 pm, 4:00 pm – 5:30pm,

Fridays 11:00am-12:00pm

and by appointment

 

Lecture Times & Location:               Mondays and Wednesdays 02:30 PM-03:45 PM @ GUA 2204

 

Recommended Text:

[1]  D. A. Hodges, H. G. Jackson, and R. A. Saleh, Analysis and Design of Digital Integrated Circuits in Deep Submicron Technology. 3rd Ed.

[2]  Complimentary course handouts.

 

Reference Books:

[1]  J. P. Uyemura, Introduction to VLSI Circuits and Systems, John Wiley & Sons, 2002.

[2]  M. J. S. Smith, Application-Specific Integrated Circuits. Reading, MA: Addison-Wesley, Longman, 1997.

[3]  R. J. Baker, H. W. Li and D. E. Boyce, CMOS Circuit Design, Layout, and Simulation. IEEE Press, 1997.

[4] Rabaey et. al., Digital Integrated Circuits, Uppper Saddle River, NJ: Prentice-Hall, 2nd ed.

 

Topics to be covered:

(1) Digital systems and VLSI

(2)  Fabrication process, transistors, wires and vias, design rules, layout design and tools

(3) Transistor sizing

(4) Logic styles

(5) Combinational logic networks: Layout design methods, simulation, combinational  network delay, crosstalk, power optimization, switch logic network, combinational network testing

(6)  Sequential machines: latches and flip-flops, clocking, sequential system design.

(7) Subsystem design: memories and/or ALUs

(8) Interconnect Design Issues: interconnect delays, modeling, power grid design, clock design

(9) VLSI testing: fault models, test pattern generation, fault simulation, fault coverage, design for testability

(10) Design projects

 

Grading scheme for EE427 students:

Homeworks                           25%

Design project                     30% (20% design + 5% report + 5% oral presentation/demo)

Literature study                    15% (5+ page report (including illustrations): single column, single space, font size 10- 12)

Final                                      30% (open book, open notes in-class 2-hr exam)

 

Grading scheme for ECG 615 students:

Homeworks                           10%

Design project                      30% (20% design + 5% report + 5% oral presentation/demo)

Literature study                    30% (10+ page report (including illustrations): single column, single space, font size 10- 12)

Final                                       30% (open book, open notes in-class 2-hr exam)

 

On-line Course Information:

Course Web Page: EE427_ECG615.htm

Check this site for homework assignments, notes, laboratories and other information.

 

Lecture Notes and HW

Posting Date

Due Date

Lecture 01 Introduction

08/15/2010

 

Lecture 02 MOS Transistors

08/27/2010

 

Lecture 03 Fabrication, Layout, and Simulation

09/05/2010

 

Lab Tutorial (Part I)

09/15/2010

09/26/2010 revised

 

Lecture 04 MOS Inverter Circuits

09/20/2010

 

Lecture 05 Static MOS Gate Circuits

09/26/2010

 

Lab Tutorial (complete)

09/28/2010

 

Lecture 06 High-Speed CMOS Logic Design

10/03/2010

 

Course Project

10/12/2010

12/03/2010

 Lecture 07 Transfer Gate and Dynamic Logic Design

10/12/2010

 

Lecture 08 ALU Design

10/17/2010

 

Lecture 09 Semiconductor Memories

10/28/2010

 

Lecture 10 Interconnect Design

10/30/2010

 

Lecture 11 VLSI Testing

10/30/2010

 

 

Other Policies

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An example of academic misconduct is plagiarism: “Using the words or ideas of another, from the internet or any source, without proper citation of the sources.” See the “Student Academic Misconduct Policy” (approved December 9, 2005, located at <http://studentlife.unlv.edu/judicial/misconductPolicy.html>).

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The University requires all members of the University Community to familiarize themselves and to follow copyright and fair use requirements. You are individually and solely responsible for violations of copyright and fair use laws. The University will neither protect nor defend you nor assume any responsibility for employee or student violations of fair use laws. Violations of copyright laws could subject you to federal and state civil penalties and criminal liability, as well as disciplinary action under University policies. To familiarize yourself with copyright and fair use policies, you are encouraged to visit the following website: <http://www.unlv.edu/committees/copyright/>.

 

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The Disability Resource Center (DRC) coordinates all academic accommodations for students with documented disabilities. The DRC is the official office to review and house disability documentation for students, and to provide them with an official Academic Accommodation Plan to present to the faculty if an accommodation is warranted. Faculty should not provide students accommodations without being in receipt of this plan.

UNLV complies with the provisions set forth in Section 504 of the Rehabilitation Act of 1973 and the Americans with Disabilities Act of 1990, offering reasonable accommodations to qualified students with documented disabilities. If you have a documented disability that may require accommodations, you will need to contact the DRC for the coordination of services. The DRC is located in the Student Services Complex (SSC), Room 137, and the contact numbers are: VOICE (702) 895-0866, TTY (702) 895-0652, FAX (702) 895-0651. For additional information, please visit: <http://studentlife.unlv.edu/disability/>.

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Grading / Exams / Grade Posting – All syllabi should clearly indicate processes for grading, exams and grade posting.

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One-on-one or small group assistance with writing is available free of charge to UNLV students at the Writing Center, located in CDC-301. Although walk-in consultations are sometimes available, students with appointments will receive priority assistance.

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