University of Nevada, Las Vegas Department of Electrical and Computer Engineering |
EE 421/ECG 621
Digital Integrated Circuit Design
Summer 2017
CATALOG DATA:
An
introduction to the design, layout, and simulation of digital integrated
circuits. MOSFET
operation and parasitics. Digital
design fundamentals including the design of digital logic blocks.
Prerequisites:
CpE100 and EE320
Recommended Textbooks:
[1]
Jan. M. Rabaey, A. Chandrakasan
and B. Nikolic. Digital Integrated Circuits.
[2]
M. J. S. Smith. Application-Specific Integrated Circuits.
[3]
R. Jacob Baker. CMOS Circuit Design, Layout, and Simulation.
[4]
N. H Weste and D. Harris. CMOS VLSI Design: A
Circuits and Systems Perspective.
[5]
D. A. Hodges, H. G. Jackson, and R. A. Saleh, Analysis and Design of Digital
Integrated Circuits in Deep Submicron Technology.
[6] Niraj K. Jha and C. Chen.
Nanoelectronic Circuit
Design.
CLASS
SCHEDULE:
(1) Very intense class. Attendance is a must.
(2) The students need to take the EE421L lab to
learn computer tools for projects and homework, beginning in the first week.
(3) A homework assignment will be given on
Thursday every week, with a total of 3-4 homework assignments.
(4) A modest design project will be announced at
the end of Week 2 or the beginning of Week 3. Students can work individually or
as a team of 2.
(5) A final exam will be given on July 7, 2017
for two hours.
Lecture
Notes and Homework Assignments:
Click
here for the homework assignments and solutions (to be announced)
Lecture Notes |
Posting Date |
5/24/2017 |
|
5/24/2017 |
|
5/24/2017 5/30/2017 (updated) |
|
5/26/2017 |
|
5/30/2017 6/14/2017 (updated) |
|
5/30/2017 |
|
5/30/2017 |
|
5/30/2017 |
|
6/5/2017 |
|
6/5/2017 7/3/2017 (updated) |
|
6/20/2017 |
|
6/20/2017 |
(1) Digital systems and VLSI.
(2) Fabrication process, transistors, wires and vias,
design rules, layout design and tools.
(3) Transistor sizing.
(4) Logic styles.
(5)
Combinational logic networks: Layout design methods, simulation, combinational network
delay, crosstalk, power optimization, switch logic network.
(6)
Sequential machines: latches and flip-flops, clocking, sequential system
design.
(7) Subsystem design: memories and/or
ALUs.
(8) Interconnect Design
Issues: interconnect delays, modeling, power grid design, clock
design.
(9) VLSI testing:
fault models, test pattern generation, fault simulation, fault coverage, design
for testability.
(10) Design
projects.
EVALUATION:
For EE421 students:
Class Attendance =
5%
Homework =
20%
Design Project =
30% (25% design + 5% report)
Final Exam =
45% (open book, open notes)
Total =100%
For ECG621 students:
Class Attendance =
5%
Homework =
10%
Design Project =
30% (25% design + 5% report)
Literature
Study
= 10% (5+ page report (including illustrations): single column,
single space, font size
12)
Final Exam =
45% (open book, open notes)
Total =100%
CONTACT:
Email: yingtao.jiang@unlv.edu
Phone: 702-895 2533
OFFICE
HOURS:
Monday/Tuesday/Wednesday/Thursday
10:00am -12:30pm or by appointment |
Office location: TBE B322
Class
Meeting Time and Venue:
Monday/Tuesday/Wednesday/Thursday
1:00 pm -2:30pm |
Location: BHS 211
COURSE
WEBSITE:
URL: http://www.ee.unlv.edu/~yingtao/2017_Summer/EE421/EE421ECG621-syllabus.htm
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