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University of Nevada, Las Vegas Department of Electrical and Computer Engineering |
EE 421 Digital
Electronics
SPRING 2011
CATALOG DATA:
Digital circuit
analysis. Discrete and integrated circuit technology, logic families, A/D-D/A
circuits, comparators, Schmitt triggers.
Prerequisites:
CpE 100 and EE 320
TEXTBOOK:
[1]
Digital Integrated Circuits, Thomas A. DeMassa and
Zack Ciccone, John Wiley & Sons, ISBN
0-471-10805-7.
[2]
Course handouts.
COURSE
OBJECTIVES:
CLASS
SCHEDULE:
MW 5:30 PM 每 6:45 PM @ CBC-C122
Lecture
Notes and Homework Assignments:
Click me to get the homework
solution
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01/14/2011 |
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01/14/2011 |
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01/14/2011 |
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01/14/2011 |
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01/14/2011 |
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Homework #1 (1) Solve Example 1 in Lecture 1. (2)
Design a decimal counter
(modulo-10 counter) with the counting sequence (0,1,2,3,4,5,6,7,8,9,0,1,...).
You can use only SR FFs. Show the state diagram and minimized state table.
From the state table, derive the simplified output function and excitation
functions using the K-maps. (3)
Use JK FFs to design a majority
checker that compares the number of 1s with the number of 0s in the 3-bit
input sequence. |
01/19/2011 |
01/24/2011 |
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01/27/2011 |
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01/27/2011 |
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01/27/2011 |
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01/27/2011 |
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01/27/2011 |
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01/27/2011 |
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03/09/2011 |
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03/09/2011 |
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03/09/2011 |
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03/09/2011 |
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03/09/2011 |
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03/20/2011 |
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03/20/2011 |
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03/20/2011 |
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03/20/2011 |
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Lecture 22 Digital to Analog and Analog
to Digital Converters |
03/20/2011 |
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03/20/2011 |
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Lecture 24 Signal Integrity Basics for High
Speed/High Density Designs |
03/20/2011 |
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1.
PROPERTIES OF DIGITAL CIRCUITS: inverting and noninverting
gates, ideal logic elements, voltage transfer characteristic (VTC), logic
swing, transition width, noise, fan-in, fan-out, transient characteristics,
rise and fall times, power dissipation, power-delay product.
2.
BIPOLAR JUNCTION TRANSISTORS (BJTs): junction isolated and oxide
isolated NPNs, multi-emitter, Schottky-clamped,
lateral PNP, Ebers-Moll model, BJT modes of operation, SPICE model, IC
resistors and diodes.
3.
INTRODUCTION TO BJT DIGITAL CIRCUITS: analysis, BJT inverter,
power dissipation.
4.
RESISTOR-TRANSISTOR LOGIC (RTL): inverter and noninverter,
NOR gate, NAND gate, fan-out, power dissipation, active pull-up SPICE
simulation.
5.
DIODE TRANSISTOR LOGIC (DTL): inverter, modified DTL, BJT
modified, NAND gate, fan-out, power dissipation, SPICE simulation.
6.
TRANSISTOR-TRANSISTOR LOGIC (TTL): inverter, charge removal, NAND
gate, totem pole output, VTC, fanout, power
dissipation, open collector, low power, high speed, SPICE simulation.
7.
SCHOTTKY TRANSISTOR-TRANSISTOR LOGIC (STTL): Schottky
diodes, Schottky BJTs, STTL inverter, NAND gate, VTC,
fan-out, power dissipation, NAND GATE, low power LSTTL, SPICE simulation.
8.
OTHER TTL GATES:AND gates, NOR gates, OR gates, AOI gates, XOR
gates, Schmitt inverters and NAND gates, tri-state buffers.
9.
EMITTER-COUPLED LOGIC (ECL): BJT current switch, VTC, NOR/OR gate,
output buffers, MECL I, fan-out, power dissipation, SPICE simulation.
TEMPERATURE COMPENSATING ECL: MECL II, bias network, fan-out, power
dissipation, SPICE simulation.
10.
MORE ECL: MECL III, ECL 10K, ECL100K, power dissipation, SPICE
simulation. OTHER ECL GATES: NOR/OR gates, collector dotting, series gating,
NAND/AND gates, complex OR-AND gates, XNOR/XOR gates Schmitt triggers.
11.
MOSFETs: metal gate, silicon gate, N-channel & P-channel,
modes of operation, transconductance parameter,
threshold voltage, capacitance, SPICE model, CMOS devices.
12.
RESISTOR LOADED NMOS INVERTER: operation, graphical determination
of VTC, calculation of critical voltages, power dissipation, SPICE simulation.
SATURATED ENHANCEMENT-ONLY LOADED NMOS INVERTER: operation, graphical
determination of VTC, calculation of critical voltages, power dissipation,
SPICE simulation.
13.
LINEAR E-O LOADED NMOS INVERTER: operation, graphical
determination of VTC, calculation of critical voltages, power dissipation,
SPICE simulation
14.
ENHANCEMENT-DEPLETION LOADED NMOS INVERTER: operation, graphical
determination of VTC, calculation of critical voltages, power dissipation,
SPICE simulation.
15.
NMOS GATES: NOR, NAND, OR, AND, AOIs, XOR/XNOR, other gates, trans
gates, Schmitt inverter.
16.
CMOS INVERTER: operation, power dissipation, graphical determination
of VTC, calculation of critical voltages, design of symmetric inverter or
minimum size, inverter capacitance, dynamic response, SPICE simulation,
latch-up, input clamping. CMOS dynamic response and CMOS Fan-out
17.
CMOS COMBINATIONAL LOGIC GATES: NAND, NOR, AND, OR, AOI, XOR/XNOR
18.
CMOS TRI-STATE LOGIC GATES: high impedance Z-states, contention
X-states, tri-state inverters, applications, transmission gates.
19.
CMOS SCHMITT TRIGGER GATES: inverter, operation and VTC, design,
buffered, output, feedback, NAND gate.
20.
CMOS DRIVERS: cascaded inverters driving a load cap, multi-stage
inverter driver. DYNAMIC CMOS.
21.
A/D and D/A converters
22.
Semiconductor Memories
23.
Interconnect
EVALUATION:
Assignments + PSpice
Simulation (5) =
25% (submit all assignments)
Project (1) =
25%
Midterm (1) =
25% (to be announced)
Final (1) =
25%
Total =100%
Grades are assigned based on overall
class performance. Final grade of the student will be based on the top score in
this course. You＊ll need 50% to pass this course.
CONTACT:
Email: yingtao@egr.unlv.edu Phone: 702-895 2533
OFFICE
HOURS:
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MW 10:30am - 11:30pm |
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MW 4:00pm - 5:30pm or by appointment |
COURSE
WEBSITE:
URL: http://www.ee.unlv.edu/~yingtao/2010_Spring/ee421
PS:
You are
required to submit PSPICE simulations for Design Assignments and the PROJECT,
without which your work will not be evaluated.
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