Venkatesan Muthukumar's Publications:

 

Refereed Journal:

 

[1] Venkatesan Muthukumar, Bharath Radhakrishnan and Henry Selvaraj. Multiple Voltage and Frequency Scheduling for Power Minimization. In review for Journal of Systems Architecture, Euromicro Journal.

 

[2] Muthukumar Venkatesan and Daggu Venkateshwar Rao. Image Processing  Algorithms on Reconfigurable Architecture using HandelC. In review for Journal of Embedded Computing, Cambridge International Science Publishing (CISP).

 

[3] Venkatesan Muthukumar. An Improved Representation of Functions for Partition Based Functional Decomposition. Submitted to Applicable Algebra in Engineering, Communication and Computing Journal, IOSPress.

 

Books:

[1] Henry Selvaraj and V. Muthukumar. (2002) The Proceedings of the 15th International Conference on Systems Engineering.

 

Thesis:

[1] Muthukumar, V. (2000). New Approaches for Partition based Functional Decomposition.   Ph. D. Thesis.

[2] Muthukumar, V. (1997). Parallel Decomposition of Binary and Multiple Valued Functions. Masters Thesis.

 

Refereed Journal/Web Publications and Book Chapters:

 

[1] Venkateshwar Rao Daggu and Muthukumar Venkatesan. (2004). Design and Implementation of an Efficient Reconfigurable Architecture for Image Processing Algorithms using Handel-C. Celoxica Inc. research papers. < http://www.celoxica.com/techlib/files/CEL-W040414XQ7-281.pdf>

 

[2] Muthukumar Venkatesan and Daggu Venkateshwar Rao. (2004). Hardware Acceleration of Edge Detection Algorithm on FPGAs. Celoxica Inc. research papers.

< http://www.celoxica.com/techlib/files/CEL-W040414XRZ-282.pdf>

 

 

Publications in Press:

 

[1] Daggu Venkateshwar Rao and Muthukumar Venkatesan (2004). An Efficient Reconfigurable Architecture and Implementation of Edge Detection Algorithm using Handle-C. In the proceedings of the International Conference on Information Technology: Coding and Computing (ITCC04), April 4-7, 2004.

 

[2] J. Li, L. Gewali, H. Selvaraj, and V. Muthukumar (2004). Hybrid Greedy/Face Routing for Ad-Hoc Sensor Network. In the proceedings of the DSD Euromicro 2004 (DSD), Sept, 2004.

 

[3] M. Sherwood L. Gewali, H. Selvaraj, and V. Muthukumar. (2004). A Fast and Simple Algorithm for Computing M Shortest Paths in Stage Graph. In the Proceedings of the XV INTERNATIONAL CONFERENCE ON SYSTEMS SCIENCE SYSTEMS SCIENCE XV, September 7 - 10, 2004, Wroclaw, Poland

 

[4] Muthukumar Venkatesan and Daggu Venkateshwar Rao. (2004). Image Processing Algorithms on Reconfigurable Architecture using HandelC. In the proceedings of the DSD Euromicro 2004 (DSD), Sept, 2004.

 

Publications is Review:

 

[1] Venkatesan Muthukumar, Bharath Radhakrishnan, Henry Selvaraj (2003) Multiple Voltage And Frequency Scheduling For Power Minimization. Journal of System Architecture, Elsevier.

 

 

Presentations (3 years):

 

[1] Implementation of Large Neural Networks using Decomposition. In The 2002 International Conference on Mathematics and Engineering Techniques in Medicine and Biological Sciences (METMBS '02)

 

[2] Partition based Functional Decomposition Tool for FPGAs, V. Muthukumar. Published in 15th International Conference on Systems Engineering will be held in Las Vegas, NV.

 

[3] Comparison of Heuristic Algorithms for Variable Partitioning in Circuit Implementation - The Sixteenth International Conference on VLSI Design, New Delhi, India, 2003

 

[4] Alternate Path Routing Algorithm for Traffic Engineering in the Internet - The International Conference on Information Technology: Coding and Computing (ITCC03), April 28-30, 2003.

 

Conference Papers:

 

[1] Bharath Radhakrishnan, Muthukumar Venkatesan (2003). Multiple Voltage and Frequency Scheduling for Power Minimization. In the proceedings of EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN (DSD) - Architectures, Methods and Tools, Belek near Antalya, Turkey, September 1 – 6, 2003

[2] Ling Wang, Yingtao Jiang, Henry Selvaraj, Muthukumar Venkatesan (2003). A Synthesis Scheme for Low Power Designs with Multiple Voltages under Timing Constraints. In the proceedings of the 11th Annual NASA Symposium on VLSI Design, Moscow, Idaho 2003.

[3] V. Muthukumar and Henry Selvaraj (2003). Comparison of Heuristic Algorithms for Variable Partitioning in Circuit Implementation. In the proceedings of The Sixteenth International Conference on VLSI Design, , New Delhi, India, 2003.

[4] Shyam Subramanian, V. Muthukumar (2003). Alternate Path Routing Algorithm for Traffic Engineering in the Internet. In the proceedings of the International Conference on Information Technology: Coding and Computing (ITCC03), April 28-30, 2003.

[5] S.Subramanian, V.Muthukumar (2002). Alternative Path Routing Algorithm for Traffic Engineering. In the proceedings of the 15th International Conference on Systems Engineering will be held in Las Vegas, NV.

[6] G.Cherussery, H.Selvaraj, V. Muthukumar (2002). A Bi-level patitioning of a circuit into multi-FPGAs. In the proceedings of Work in Progress Session of the EUROMICRO /DSD conference event in Dortmund, September 4-6, 2002

[7] Muthukumar, V., Selvaraj, H. (2002). A Heuristic Algorithm to Variable Patitioning in Functional Decomposition. In the proceedings of Work in Progress Session of the EUROMICRO /DSD conference event in Dortmund, September 4-6, 2002.

[8] G.Cherussery, H.Selvaraj, V. Muthukumar, P.Sapiecha (2002). A multi-way partitioning of a circuit into multi-FPGAs. In the proceedings of the 15th International Conference on Systems Engineering will be held in Las Vegas, NV.

[9] H. Selvaraj, H. Niewiadomski, P. Buciak, M. Pleban, P. Sapiecha, T. Luba and V. Muthukumar. (2002) Implementation of Large Neural Networks using Decomposition. In The 2002 International Conference on Mathematics and Engineering Techniques in Medicine and Biological Sciences (METMBS '02)

[10] Emma Regentova, Muthukumar, V., Henry Selvaraj, Shahram Latifi. (2002) Integrated research/educational knowledge base for a new computer engineering curriculum. In The 5th IASTED International Multi-Conference Computers and Advanced Technology in Education (CATE 2002) Cancun, Mexico

[11] Muthukumar, V. and Emma Regentova (2002). Combined research and curriculum development. Accepted in The International Conference on Engineering Education, Manchester, UK.

[12] Muthukumar, V. (2002) Partition based Functional Decomposition Tool for FPGAs, V. Muthukumar. Accepted in 15th International Conference on Systems Engineering will be held in Las Vegas, NV.

[13]  Muthukumar, V. (2001). An improved input-output encoding approach for functional decomposition. In the proceedings of Digital Systems Design Symposium (DSD'01), Warsaw, Poland.

[14] Muthukumar, V., Selvaraj, H., Bignall, R. J. (2001). An improved representation of functions for partition based functional decomposition. In the Proceedings of the International Conference on Computational Intelligence and Multimedia Applications - 2001, Japan.

[15] Muthukumar, V., Bignall, R.J., Selvaraj, H. (2000). An Efficient Input-Output Encoding Approach for Serial Decomposition. In the proceedings of Brazilian Symposium on Integrated Circuit Design (SBCCI’00), Brazil.

[16] Muthukumar, V., Bignall, R.J., Selvaraj, H. (2000). Search Heuristic Algorithm for R-Admissibility based Variable Partition Method in Functional Decomposition. In the proceedings of IEEE International Symposium on Circuits and Systems ISCAS’01 May, 2001 Sydney, Australia

[17] Muthukumar, V., Bignall, R.J., Selvaraj, H. (2000). An Improved Column minimization Approach for Partition-based Functional Decomposition. In the proceedings of Digital Systems Design Symposium (DSD'00), Maastricht, The Netherlands.

[18] Selvaraj, H., Muthukumar, V., Bignall, R.J., Verma, B. (1999) Functional Decomposition for FPGA Based Designs: A Weighted Graph Approach for Encoding of Compatible Classes. In the Proceedings of the International Conference on Computational Intelligence and Multimedia Applications - 1999, New Delhi, India.

[19] Selvaraj, H., Muthukumar, V. (1998). A Reconfigurable Printed Character Recognition System Using A Logic Synthesis Tool. In the Proceedings of the Euromicro Workshop on Digital Systems - 1998, Vasteras, Sweden.

[20] Muthukumar, V., Selvaraj, H., Bignall, R. J. (1998). Character recognition using functional decomposition. In the Proceedings of the International Conference on Computational Intelligence and Multimedia Applications - 1998, Gippsland, Australia.

[21] Muthukumar, V., Selvaraj. H., Bignall R.J. (1997). Parallel Decomposition of Multiple Valued Functions and its Application in Information Systems. In the Proceedings of the International Conference on Computational Intelligence and Multimedia Applications - 1997, Gold Coast, Australia.

[22] Muthukumar, V., Selvaraj, H., Bignall, R.J. (1996). Parallel Decomposition of Binary Valued Functions - Selection of Dependent Inputs by Elimination of Contradiction. In the Proceedings of International Workshop on Logic and Architecture Synthesis - 1996, Gernoble, France.

[23] Selvaraj, H., Bignall, R.J.,  Muthukumar, V. (1996). Selection of Candidate Variables by Rejection for Disjoint Serial Decomposition. In the Proceedings of International Workshop on Logic and Architecture Synthesis - 1996, Gernoble, France.

 

Unreferred Publications:

 

[1] Selvaraj H., Bignall R.J., Venkatesan M. Selection of Candidate Variables for Disjoint Serial Decomposition, Research Report 10/96, GSCIT, Monash University, 1996.

 

[2] Venkatesan M., Selvaraj H., Bignall R.J. Parallel Decomposition of Binary Valued Functions - Selection of Dependent Inputs by Elimination of Contradictions, Research Report 12/96, GSCIT, Monash University, 1996.

 

[3] Venkatesan M., Selvaraj H., Bignall R.J. Parallel Decomposition of Binary Valued Functions-Selection of Dependent Inputs by Elimination of Contradictions, Information Technology Research, GSCIT Research Center, Monash University, 1996.