List of References

1. Topologies:

Sorting Networks

M. Adler, J.W. Byers, and M. Richard, "Parallel sorting with limited bandwidth," SIAM J. Comput., vol. 29, no. 6, pp. 1997-2015, 2000.
M. Ajtai, J. Komlós, and E. Szemerédi, "Sorting in $c\,{\rm log}\,n$ parallel steps," Combinatorica, vol. 3, no. 1, pp. 1-19, 1983.
*M. Ajtai, J. Komlós, and E. Szemerédi, "An O(n logn) sorting network," in Proc. 15th annual ACM symposium on Theory of Computing, 1983, pp. 1-9.
E. Dyer, E. Martin, and S. Sen, "Fast and optimal parallel multidimensional search in PRAMs with applications to linear programming and related problems," SIAM J. Comput., vol. 30, no. 5, pp. 1443-1461, 2000.
*M. Kutylowski, K. Lorys, B. Oesterdiekhoff, and R. Wanka, "Periodification scheme: constructing sorting networks with constant period," J. ACM, vol. 47, no. 5, pp. 944-967, Sept. 2000.
T. Leighton and C.G. Plaxton, "Hypercubic sorting network," SIAM J. Comput., vol. 27, no. 1, pp. 1-47, 1998.

Selection Networks

M. Adler, J.W. Byers, and M. Richard, "Parallel sorting with limited bandwidth," SIAM J. Comput., vol. 29, no. 6, pp. 1997-2015, 2000.
N. Pippenger, "Selection networks," SIAM J. Comput., 20 (1991), no. 5, 878-887.
S. Jimbo and A. Maruoka, "A method of constructing selection networks with O(log n) depth," SIAM J. Comput., vol. 25, no. 4, 709-739, 1996.

Strictly Nonblocking Networks

S.-P. Chung and K.W. Ross, "On nonblocking multirate interconnection networks," SIAM J. Comput., vol. 20, no. 4, pp. 726-736, 1991.
P. Feldman, J. Friedman, and N. Pippenger, "Wide-sense nonblocking networks," SIAM J. Discrete Math., vol. 1, no. 2, pp. 158-173, 1988.
Fingerhut, J. Andrew, S. Suri, and J.S. Turner, "Designing least-cost nonblocking broadband networks," J. Algorithms, vol. 24, no. 2, pp. 287-309, 1997.
J. Friedman, "A lower bound on strictly nonblockingnetworks," Combinatorica, vol. 8, no. 2, pp. 185-188, 1988.
P. Fishburn, F.K. Hwang, D.Z. Du, and B. Gao, "On 1-rate wide-sense nonblocking for 3-stage Clos networks," Discrete Appl. Math., vol. 78, no. 1-3, pp. 75-87, 1997.
F.K. Hwang, "Three-stage multiconnection networks which are nonblocking in the wide sense," Bell System Tech. J., vol. 58, no. 10, pp. 2183-2187, 1979.
F.K. Hwang, "Three-stage multiconnection networks which are nonblocking in the wide sense," Bell System Tech. J., vol. 58, no. 10, pp. 2183-2187, 1979.
R. Melen and J.S. Turner, "Nonblockingmultirate networks," SIAM J. Comput., vol. 18, no. 2, pp. 301-313, 1989.
N. Pippenger, "On rearrangeableand nonblocking switching networks," J. Comput. System Sci., vol. 17, no. 2, pp. 145-162, 1978.
D.G. Smith, "Lower bound on the size of a 3-stage wide-sense nonblocking network," Electron. Lett., vol. 13, no. 7, pp. 215-216, 1977.
Y. Yang and J. Wang, "Wide-sense nonblocking Clos networks under packing strategy," IEEE Trans. Comput., vol. 48, no. 3, pp. 265-284, 1999.
C. Zhou and Y. Yang, ''Wide-sense nonblocking multicast in a class of regular optical WDM networks,'' IEEE Trans. Commu., vol. 50, no. 1, pp. 126-134, Jan. 2002.

Charactering Indirect Network Topologies

G.J. Chang, F.K. Hwang, and L.D. Tong, "Characterizing bit permutation networks," Networks, vol. 33, no. 4, pp. 261-267, 1999.
F.K. Hwang, and C.-H. Yen, "Characterizing bit permutation networks obtained from the line digraphs of bit permutation networks", Networks, vol. 38, no. 1, pp. 1-5, 2001.

2. Switching:

M. Lee and C.L. Wu, "Performance analysis of circuit switching, baseline interconnection networks," in Proc. 11th Int'l Symp. Computer Architecture, 1984, pp. 82-90.
J.S. Kim, "Performance study of packet switching multistage interconnection networks," ETRI J., vol. 16, no. 3, pp. 27-41, Oct. 1994.
A. Tentov and A. Grnarov "Performance analysis of packet switching interconnection networks with finite buffers," in Proc. EUROMICRO, 1996, pp. 390-396.
D.L. Willick and D.L. Eager, "An analytical model of multistage interconnection networks," in Proc. ACM SIGMETRICS, 1990, pp. 192-202.
K.J. Liszka, J.K. Antonio, and H.J. Siegel, "Is an alligator better than an armadillo?," in IEEE Concurrency, vol. 5, no. 4, pp. 20-28, Oct.-Dec. 1997.
K.J. Liszka, J.K. Antonio, and H.J. Siegel, "Is an alligator better than an armadillo?," in IEEE Concurrency, vol. 5, no. 4, pp. 20-28, Oct.-Dec. 1997.

3. Routing:

M. Andrews, A. Fernández, M. Harchol-Balter, T. Leighton, L. Zhang, "General dynamic routing with per-packet delay guarantees of $O({\rm distance}+1/{\rm session rate})$," SIAM J. Comput., vol. 30, no. 5, pp. 1594-1623, 2000.
M. Andrews and L. Zhang, "Packet routing with arbitrary end-to-end delay requirements," in Proc. 31st ACM Symp. Theory of Computing, 1999.
S. Arora, F.T. Leighton, and B.M. Maggs, "On-line algorithms for path selection in a nonblocking network," SIAM J. Comput., vol. 25 no. 3, pp. 600-625, 1996.
H.D.L. Hollmann and J. H. van Lint, "Nonblocking self-routing switching networks," Discrete Appl. Math., vol. 37/38, pp. 319--340, 1992.
F. T. Leighton, B. M. Maggs, and S. B. Rao, "Packet routing and job-shop scheduling in $O(congestion + dilation)$ steps," Combinatorica, vol. 14, pp. 167-186, 1994.
G. Lin and N. Pippenger, "Parallel algorithms for routing in nonblocking networks," in Proc. ACM Symp. Parallel Algorithms and Architectures, 1991, pp. 272-277.
T.H. Szymanski, "Design principles for practical self-routing nonblocking switching networks with O(NlogN) bit-complexity," IEEE Trans. Computers, vol. 46, no. 10, pp. 1-13, Oct. 1997.

4. Multicasting in several topologies:

Bar-Noy, S. Guha, J. Naor, and B. Schieber, "Multicasting in heterogeneous networks," in Proc. STOC, 1998.
R. Caceres, N.G. Duffield, J. Horowitz, F. Lo Presti, and D. Towsley, "Loss-based inference of multicast network yopology," in Proc. IEEE CDC, 1999.
S. McCanne, V. Jacobson, and M. Vetterli, "Receiver-driven layered multicast," in ACM SIGCOMM, August 1996, Stanford, CA, pp. 117-130.
S. Paul, K. K. Sabnani, J. C. Lin, and S. Bhattacharyya, "Reliable multicast transport protocol (RMTP),"IEEE J. Special Areas in Communications (JSAC), vol. 15, no. 3, pp.407-421, Apr. 1997.
S. Ratnasamy and S. McCanne,"Inference of multicast routing trees and bottleneck bandwidths using end-to-end measurements,"in Proc. INFOCOM, 1999.
L. Vicisano, J. Crowcroft, and L. Rizzo,"TCP-like congestion control for layered multicast data transfer," in Proc. IEEE INFOCOM, 1998.
Y. Yang, "A new self-routing multicast network," IEEE Trans. on Parallel and Distributed Computing Systems (PDCS), vol 10, no. 11, Dec. 1999.
Y. Yang, "A class of interconnection networks for multicasting,"IEEE Trans. Computers, vol. 47, no. 8, pp. 899-906, Aug. 1998.
Y. Yang, J. Wang, and C. Qiao, "Nonblocking WDM multicast switching networks,''IEEE Trans. PDCS, vol. 11, no. 12, pp. 1274-1287, Dec. 2000.
Y. Yang, "The performance of multicast banyan networks,'' J. Parallel and Distributed Computing, vol. 60, no. 8, pp. 909-923, Aug. 2000.
Yang and G.M. Masson, "The necessary conditions for Clos-type nonblocking multicast networks," IEEE Trans. Comput., vol. 48, no. 11, pp. 1214-1227, 1999.

5. Flow control and load balancing:

M. Adler, A.L. Rosenberg, R.K. Sitaraman, and W. Unger, "Scheduling time-constrained communication in linear networks," in Proc.10th ACM Symp. Parallel Algorithms and Architectures (SPAA), 1998.
M. Adler, S. Khanna, R. Rajaraman, and A. Rosen,"Time-constrained scheduling of weighted packets on trees and meshes," in Proc.11th ACM SPAA , 1999.
J. Kleinberg, Y. Rabani, and E. Tardos, "Fairness in routing and load balancing," in Proc. 40th IEEE Symp. Foundations of Computer Science (FOCS), 1999.
K. Parekh and R. G. Gallager, "A generalized processor sharing approach to flow control in integrated services networks: The single-node case," IEEE/ACM Trans. Networking, vol. 1, no. 3, pp. 344-357, 1993.
K. Parekh and R. G. Gallager, "A generalized processor sharing approach to flow control in integrated services networks: The multiple-node case," IEEE/ACM Trans. Networking, vol. 2, no. 2, pp. 137-150, 1994.

6. Fault-tolerance and reliability:

L. Barrière, J. Fàbrega, E. Simó, and M. Zaragozá, "Fault-tolerant routings in chordal ring networks," Networks, vol. 36, no. 3, pp. 180-190, 2000.
M.-S.Chen and K.G. Shin, "Adaptive fault-tolerant routing in hypercube multicomputers," IEEE Trans. Comput., vol. 39, no. 12, pp. 1406-1416, 1990.
F. Chong, E. Egozy, A. DeHon, "Fault tolerance and performance of multipath multistage interconnection networks," Advanced Research in VLSI and Parallel Systems, pp. 227-242, MIT Press, Mar. 1992.
A. DeHon, T.F. Knight Jr., and H. Minsky, "Fault-tolerant design for multistage routing networks," in Proc. Int'l Symp. Shared Memory Multiprocessing, 1991, pp. 60-71.
L. Gargano, U. Vaccaro, and A. Vozella, "Fault tolerant routing in the star and pancake interconnection networks," Inform. Process. Lett., vol. 45, no. 6, pp. 315-320, 1993.
C.-N. Hung, L.H. Hsu, and T.-Y. Sung,] "On the construction of combined k-fault tolerant hamiltonian graphs,"Networks, vol 37, no. 3, pp. 165-170, 2001.
E. Kushilevitz, R. Ostrovsky, and A. Rosen, "Log-space polynomial end-to-end communication,"in Proc. 28th STOC, 1995, pp. 559-568.

M. Adler and F. Fich, "The complexity of end-to-end communication in memoryless networks," in Proc. 18th ACM Symp. Principles of Distributed Computing (PODC), 1999.
H. Shen, F. Chin, and Y. Pan, "Efficient fault-tolerant routing in multihop optical WDM networks", IEEE Trans. on Parallel and Distrib. Comput. Sys., vol. 10, no. 10, pp. 1012-1025, Oct. 1999.
A.A. Rescigno and U. Vaccaro, "Highly fault-tolerant routing in the star and hypercube interconnection networks," Parallel Process. Lett., vol. 8, no. 2, pp. 221-230, 1998.
K. Wada, Y. Luo, and K. Kawaguchi, "Optimal fault-tolerant routings for connected graphs," Inform. Process. Lett., vol. 41, no. 3, pp. 169-174, 1992.

7. Blocking Probability:

K. Wada, Y. Luo, and K. Kawaguchi, "A. Birman, "Computing approximate blocking probabilities for a class of all-optical networks, " in Proc. IEEE INFOCOM, 1995, pp651-658.
S.P. Chung, A. Kashper, and K.W. Ross, "Computing approximate blocking probabilities for large loss networks with state-dependent routing, " IEEE/ACM Transactions on Networking, vol.1, no. 1, pp. 105-115, Feb. 1993.
S.P. Chung, A. Kashper, and K.W. Ross, "M.P. Haynos and Y. Yang, " An analytical model on the blocking probability of a fault-tolerant network, " IEEE Trans. PDCS, special issue on Fault-Tolerant Routing, vol. 10, no. 10, pp. 1040-1051, Oct. 1999.
Y. Yang and J. Wang, "On blocking probability of multicast networks, " IEEE Trans. Communications , vol. 46, no. 7, pp. 957-968, July 1998., 1999.
Y. Yang and J. Wang, "A more accurate analytical model on blocking probability of multicast networks," IEEE Trans. Communications, vol. 48, no. 11, pp. 1930-1936, Nov. 2000.

8. Optical MIN and Related Algorithms:

X. Tan, M. Yang. L. Zhang, Y. Jiang, J. Yang, "A generic optical router design for photonic network-on-chips," IEEE Journal of Lightwave Technology, vol. 30, no. 3, Feb. 2012, pp. 368-376.
B.A. Small and K. Bergman, "Optimization of multiple-stage optical interconnection networks," IEEE Photon. Technol. Lett., vol. 18, no. 1, pp. 238-240, Jan. 2006.
B.A. Small, T. Kato, and K. Bergman, "Dynamic power considerations in a complete 12x12 optical packet switching fabric," IEEE Photon. Technol. Lett., vol. 17, no. 11, pp. 2472-2474, Nov. 2005.
E. Lu and S. Q. Zheng, "Parallel routing algorithms for nonblocking electronic and photonic switching networks," IEEE Trans. PDCS, vol. 16, no. 8, pp. 702-713, Aug, 2005.
E. Lu, M. Yang, B. Yang, and S. Q. Zheng, "A class of self-routing strictly nonblocking photonic switching networks," in Proc. IEEE Globecom, 2004, pp.1011-1015.
R. Chamberlain, C.S. Baw, M. Franklin, et. al, "Evaluating the performance of photonic interconnection networks," in Proc. 35th Annual Simulation Symp., 2002.
A. Rasala and G. Wilfong, "Strictly nonblocking WDM cross-connects," in Proc. SODA, pp.606--615, 2000.
Y. Yang, J. Wang, and Y. Pan, "Permutation capability of optical multistage interconnection networks," J. Parallel and Distributed Computing, vol. 60, no. 1, pp. 72-91, Jan. 2000.

9. Interconnection Networks for Network-on-Chip (NoC):

2-D Topologies

A. Ganguly, K. Chang, S. Deb, P. Pande, B. Belzer, and C. Teuscher, "Scalable hybrid wireless network-on-chip architectures for multi-core systems, " IEEE Trans. Computers, 2010, pp. 1-18.
R. Das, S. Eachempati, A.K. Mishra, V. Narayanan, and C.R. Das, "Design and Evaluation of a Hierarchical On-Chip Interconnect for Next-Generation CMPs," in Proc. 15th IEEE Symp. HPCA, 2009.
X. Tan, L. Zhang, S. Neelkrishnan, M. Yang, Y. Jiang, Y. Yang, "Scalable and fault-tolerant network-on-chip design using the quartered recursive diagonal torus topology," in Proc. 18th ACM Symp. GLVLSI, 2008.
J. Kim, W. J. Dally, and D. Abts, "Flattened butterfly: a cost-efficient topology for high-radix networks, " in Proc. Int’l Symp. Computer Architecture (ISCA), pp. 126-137, 2007.
T. Bjerregaard and S. Mahadevan, "A survey of research and practices of network-on-chip, " ACM Computing Surveys, vol. 38, Mar. 2006.
J. Balfour and W. J. Dally,"Design tradeoffs for tiled CMP on-chip networks, in Proc. 20^th Int'l Conf. Supercomputing, 2006.
P.P. Pande, C. Grecu, M. Jones, A. Ivanov, and R. Saleh, "Performance evaluation and design tradeoff for network-on-chip interconnect architectures, "” IEEE Trans. Computers, vol. 54, no. 8, Aug. 2005, pp. 1025-1040.
D. Wiklund, S. Sathe, and D. Liu, "Benchmarking of on-chip interconnection networks, " in Proc. Int'l Conf. Microelectronics (ICM), 2004.
Adriahantenaina, H. Charlery, A. Greiner, L. Mortiez, and C. Zeferino, "SPIN: a scalable packet switched on-chip micronetwork, " in Proc. Design Automation and Test Conf. - Designer's Forum, 2003, pp. 70-79.
F. Karim, A. Nguyen, and S. Dey, "An interconnect architecture for networking systems on chip, " IEEE Micro, vol. 22, no. 5, Sep.-Oct. 2002, pp. 36-45.
A. Aggarwal and M. Franklin, "Hierarchical interconnects for on-chip clustering, " in Proc. Int'l Parallel and Distributed Processing Symp. (IPDPS), 2002, pp. 602-609.
L. Benini and G. DeMicheli, "Powering networks on chips: energy-efficient and reliable interconnect design for SoCs, "in Proc. 14^th Int. Symp. System Synthesis, 2001, pp. 33-38.
P. Guerrier and A. Greiner, "A generic architecture for on-chip packet-switched interconnections, " in Design Automation and Test in Europe (DATE) Conference and Exhibition, 2000, pp. 250-256.

3-D Topologies

R. S. Ramanujam and B. Lin, "A layer-multiplexed 3D on-chip network architecture, " IEEE Embedded System Letters, vol. 1, no. 2, pp. 50-55, Aug. 2009.
A.Y. Weldezion, M. Grange, D. Pamunuwa, Z. Lu, et. al, "Scalability of network-on-chip communication architecture for 3-D meshes, " in Proc. IEEE/ACM NOCS, 2009.
V. F. Pavlidis and E. G. Friedman, "3-D topologies for networks-on-chip, " IEEE Trans. Very Large Scale Integration (VLSI), vol. 15, no. 10, pp. 1081-1090, Oct. 2007.
H. Matsutani, M. Koibuchi, and H. Amano, "Tightly-coupled multi-layer topologies for 3-D NoCs, " in Proc. Int'l Conf. Parallel Processing, Sept. 2007.
B. S. Feero and P. P. Pande, "Network-on-chip in a three-dimensional environment: a performance evaluation," IEEE Trans. Computers, vol. 58, no. 1, Jan. 2007, pp. 32-45.
H. Matsutani, M. Koibuchi, and H. Amano, "Tightly-coupled multi-layer topologies for 3-D NoCs," in Proc. Int’l Conf. Parallel Processing (ICPP), 2007.

Routing, Switching, Flow Control, Deadlock Avoidance/Recovery

A. Verma, P.S. Multani, D. Mueller-Gritschneder, V. Todorov, and U. Schlichtmann, "A greedy approach for latency-bounded deadlock-free routing path allocation for application-specific NoCs," in Proc. IEEE/ACM NOCS, 2013.
Z. Lu and Y. Wang, "Dynamic flow regulation for IP integration in network-on-chip," in Proc. IEEE/ACM NOCS, 2012.
D. Zhao and R. Wu, "Overlaid mesh topology design and deadlock free routing in wireless network-on-chip," in Proc. IEEE/ACM NOCS, 2012.
M. Ebrahimi, M. Daneshtalab, F. Farahnakian, et al.,"HARAQ: congestion-aware learning model for highly adaptive routing algorithm in on-chip networks," in Proc. IEEE/ACM NOCS, 2012.
M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, and H. Tenhunen, "Exploring partitioning methods for 3D networks-on-chip utilizing adaptive routing model," in Proc. IEEE/ACM NOCS, 2011.
S. Rodrigo, J. Flich, A. Roca, S. Medardoni, et. al,"Cost-efficient on-chip routing implementations for CMP and MPSoC systems," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 4, pp. 534-547, Apr. 2011.
X. Wang, M. Yang, Y. Jiang, and P. Liu, "On an efficient NoC multicasting scheme in support of multiple applications running on irregular sub-networks," Microprocessors and Microsystems, vol. 35, no. 2, pp. 119-129, Mar. 2011.
Lankes, T. Wild, A. Herkersdorf, S. Sonntag, and H. Reinig,"Comparison of deadlock recovery and avoidance mechanisms to approach message dependent deadlocks in on-chip networks, " in Proc. IEEE/ACM NOCS, 2010.
N. Concer, L. Bononi, M. Soulie, and R. Locatelli, "CTC: an end-to-end flow control protocol for multi-core systems-on-chip, " in Proc. IEEE/ACM NOCS, 2009.
R. Holsmark, S. Kumar, M. Palesi, and A. Mejia, "HiRA: a methodology for deadlock free routing in hierarchical network on chip, " in Proc. IEEE/ACM NOCS, 2009.
M. Yang, T. Li, Y. Jiang, and Y. Yang, "Fault-tolerant routing schemes in RDT(2,2,1)/α-based interconnection network for networks-on-chip designs," in Proc. ISPAN, 2005, pp. 52-57.

Task Scheduling, IP Mapping, Power and Thermal Management

X. Wang, T. Mak, M. Yang, Y. Jiang, M. Daneshtalab, and M. Palesi, "On self-tuning networks-on-chip for dynamic network-flow dominance adaptation,"in Proc. IEEE/ACM NOCS, 2013.
P. Bogdan, R. Marculescu, S. Jain, and R.T. Gavila, "An optimal control approach to power management for multi-voltage and frequency islands multiprocessor platforms under highly variable workloads,"in Proc. IEEE/ACM NOCS, 2013.
D. DiTomaso, A. Kodi, D. Matolak, S. Kaya, S. Laha, and W. Rayess, "Energy-efficient adaptive wireless NoCs Architecture,"in Proc. IEEE/ACM NOCS, 2013.
X. Wang, M. Palesi, M. Yang, Y. Jiang, M. Huang, and P. Liu, "Energy efficient run-time incremental mapping for 3-D networks-on-chp," in Proc. 8th Int'l Conf. Network and Parallel Computing (NPC), 2011.
X. Wang, M. Yang, Y. Jiang, and P. Liu, "A power-aware mapping approach to map IP cores onto NoCs under bandwidth and latency constraints," ACM Transactions on Architecture and Code Optimization, vol. 7, no. 1, pp. 1-30, Apr. 2010.
C.-H. Chao, K.-Y. Jheng, H.-Y. Wang, J.-C. Wu, and A.-Y. Wu, "Traffic- and thermal-aware run-time thermal management scheme for 3D NoC systems, " in Proc. IEEE/ACM NOCS, 2010.
P. Ghosh, A. Sen, and A. Hall, "Energy efficient application mapping to NoC processing elements operating at multiple voltage levels, "in Proc. IEEE/ACM NOCS, 2009.
J. Hu and R. Marculescu, "Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints, " in Proc. Europe Conf. Design, Automation and Test, 2004.
J. Hu and R. Marculescu, "Energy- and performance-aware mapping for regular NoC architectures, in Proc. DATE, pp. 233-239, 2003.

Photonic NoCs

C. Li, M. Browning, P.V. Gratz, S. Palermo, "LumiNOC: a power-efficient, high-performance, photonic network-on-chip for future parallel architectures," in Proc. IEEE/ACM NOCS, 2013.
Y. Ye, J. Xu, X. Wu, W. Zhang, X. Wang, M. Nikdasi, Z. Wang, W. Liu, and Z. Wang, "3-D mesh-based optical network-on-chip for multiprocessor system-on-chip," IEEE Trans. CAD NoCS, vol. 32, no. 4, pp. 584-595, Apr. 2013.
X. Tan, M. Yang. L. Zhang, Y. Jiang, J. Yang, "A generic optical router design for photonic network-on-chips," IEEE Journal of Lightwave Technology, vol. 30, no. 3, Feb. 2012, pp. 368-376.
R. W. Morris, A. K. Kodi, "Exploring the design of 64- and 256-core power efficient nanophotonic interconnect, " IEEE J. Selected Topics Quantum Electronics, vol. 16, no. 5, pp. 1386-1393, Sept./Oct. 2010.
L.P. Carloni, P. Pande, and X. Yuan, "Networks-on-chip in emerging interconnect paradigms: advantages and challenges," in Proc. IEEE/ACM NOCS, 2009.
H. Gu, J, Xu, W. Zhang, "A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip," in Proc. Design, Automation & Test Europe Conf. & Exhibition, Jun. 2009, pp. 3-8.
M. Petracca, B. G. Lee, K. Bergman, L. P. Carloni, "Photonic NoCs: system-level design exploration, " IEEE Micro vol. 29, no. 4, pp. 74-85, Jul. 2009.
Y. Pan, P. Kumar, J. Kim, G. Memik, Y.Zhang, A. Choudhary, "Firefly: illuminating future network-on-chip with nanophotonics, " in Proc. 36^th Int'l Symp. Computer Architecture (ISCA), 2009, pp. 429-440.
Y. Ye, L. Duan, J. Xu, J. Ouyang, M. K. Hung, Y. Xie, "3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC), " in Proc. IEEE Int’l Conf. 3D System Integration, 2009, pp. 1-6.
Joshi, C. Batten, Y. J. Kwon, S. Beamer, I. Shamim, K. Asanovic, V. Stojanovic, "Silicon-photonic clos networks for global on-chip communication, " in Proc. IEEE/ACM NOCS, 2009.
D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. P. Jouppi, M. Fiorentino, A. Davis, N. Binkert, R. G. Beausoleil, J. H. Ahn, "Corona: system implications of emerging nanophotonic technology, " in Proc. Int'l Symp. Computer Architecture, 2008.
A. Shacham, K. Bergman, L. P. Carloni, "Photonic networks-on-chip for future generations of chip multiprocessors IEEE Trans. Computers, vol. 57, no. 9, pp. 1246-1260, Sept. 2008.
A. Shacham,K. Bergman, L.P. Carloni, "On the design of a photonic network-on-chip, " in Proc. 1^st Int'l Symp. Networks-on-Chip, 2007, pp.53 – 64.