Digital System Architecture and Design

CPE300 Fall 2011

Dr. Brendan Morris,
SEB 3243
OH: MTuW 16:30-17:30

Lecture: MW 17:30-18:45, CBC C316
Final: W Dec. 14, 18:00-20:00

Textbook: Computer Systems Design and Architecture, V.P. Heuring and H. F. Jordan, 2nd Edition, ISBN: 0-13-048440-7

Catalog Description
Digital systems, ALU and CPU implementations. Data & control path design using hardware description language. Memory organization: DRAM and SRAM, Interfacing.
Prerequisites: CPE200


Midterms: 25% 10/19
Final: 30% 12/14 18:00
Project: 20% 12/05
Homework: 25%
Students may work together in study groups but all assignments must be completed individually. Homework will be due in class on the designated date. No late homeworks will be accepted unless prior notification and arrangements are made.


12/13/11 Final exam is tomorrow from 6-8pm. The exam is closed book with a single handwritten page of notes. Calculators will not be needed.
11/01/11 The project descripion [pdf] and example proposals [pdf] are now posted. Think about who you would like to partner with because the projects will be done in pairs.
10/17/11 The midterm exam will be closed book but you can bring 1 page of handwritten notes (front and back). Calculators are allowed at the exam.
09/28/11 There will be no class on Wednesday Oct 5.
09/19/11 Homework #2 deadline is extended until Wednesday 9/21.
09/15/11 Homework #2 problem 1 (H&J 2.4) has been updated. Note there is no longer an associated memory traffic component as it is contained in problem 2 (H&J 2.5).
09/13/11 Homework #2 deadline is extended until Monday 9/19.
09/08/11 Homework #2 is posted in the schedule. Homework #1 solutions will not be posted until Monday.
08/31/11 Lecture 2 slides are updated to fix typos. Please see the MC68000 Programer Reference Guide [pdf] to see how the ISA is defined. H&J refers to the textbook by Heuring and Jordan.
08/30/11 Please email the professor if you did not recieve a class confirmation email. Include "cpe300:" in the subject line to be sure it will not be missed.
Reading assignments and homeworks will be posted on the website. The first assignment will be posted on Wed. 8/31.
08/29/11 Syllabus [pdf]
Course description slides [pdf]
Introduction slides [pdf]
08/28/11 Welcome to Fall 11. First class is on Monday 8/29.


WeekDateLecture TopicReadingAssignment
1 08/29 M Course Introduction
H&J Ch 1 HW01 [pdf]
Solutions [pdf]
Due W 09/07
08/31 W Layered View of Computer
2 09/05 M Labor Day Holiday H&J Ch 2 HW02 [pdf]
Solutions [pdf]
Due W 09/21
09/07 W Instruction Set Architecture
3 09/12 M SRC, RTN, Digital Bus Logic
H&J Ch 2
09/14 W SRC, RTN, Digital Bus Logic
4 09/19 M RTN, Digital Bus Logic
H&J 3.1-3.2, 6.1 HW03 [pdf]
Solutions [pdf]
Due M 10/03
09/21 W Number Representation, Performance, CISC vs. RISC
5 09/26 M Motorola MC68000 CISC Microprocessor
H&J 3.3-3.4
09/28 W SPARC RISC Architecture
6 10/03 M Computer Arithmetic and ALU
H&J 6 HW04 [pdf]
Solutions [pdf]
Due M 10/17
10/05 W No Class
7 10/10 M Computer Arithmetic and ALU: Addition/Subtraction
H&J 6
10/12 W Computer Arithmetic and ALU: Multiply/Divide and Floating Point
8 10/17 M Midterm Review
H&J 1-3, 6
10/19 W Midterm
9 10/24 M Processor Design - Datapath design and 1-Bus
H&J 4.1-4.4, 4.5-4.8 HW05 [pdf]
Solutions [pdf]
Due W 11/02
10/26 W Processor Design - Datapath and Control design
10 10/31 M Processor Design - Control, Reset, Exceptions
Project Description [pdf]
Project Proposal Suggestions [pdf]
11/02 W Project Intro
11 10/07 M Input and Output
H&J 8 HW06 [pdf]
Solutions [pdf]
Due W 11/16
10/09 W Input and Output
12 11/14 M Pipelining and Parallelism
H&J 5 HW07 [pdf]
Solutions [pdf]
Due W 11/30
11/16 W Pipelining and Parallelism
13 11/21 Memory System Design
H&J 7
Skip Advanced Topic sections
11/23 Memory System Design: Cache
14 11/28 M Memory System Design: Virtual Memory
H&J 7.6 HW08 [pdf]
Solutions [pdf]
No Due Date
11/30 W Project/Review
15 12/05 Project Presentation
H&J all
12/07 Final Review