Digital Logic Design I

CPE100 Fall 2019

Description

Professor:
Dr. Brendan Morris,
SEB 3216
OH: MW 16:00-17:00 and TTh 12:00-13:00

Lecture: TuTh 13:00-14:15, SEB 1242
Final: Tu/Th Dec 10/12, 13:00-15:00
Look up your final exam schedule now to determine conflicts.

Grader:
Smit Patel < patels18@unlv.nevada.edu >
OH: Th 14:30-15:30, TBE-B310

Tutoring:
Engineering Tutoring Lab, TBE-A 207
CPE100 Hours:
M 10:00-16:00
Tu 10:00-14:00, 15:00-16:00
W 10:00-16:00
Th 10:00-17:00
F 10:00-17:00

Textbook

Digital Design and Computer Architecture, Harris and Harris, 2nd Edition, ISBN: 978-0123944245
Electronic version for reference only (not homework) [1st Ed. link]

Recommended Text

Fundamentals of Logic Design, Roth and Kinney, 7th Edition, ISBN: 978-1133628477

Catalog Description:

Logic gates. Simplification of Boolean functions. Design and testing of combinational and sequential circuits including code converters, multiplexers, adders, and synchronous counters.
Prerequisites: MATH 127 OR MATH 128 OR MATH 181 OR higher, OR SAT math score of 630 or higher OR ACT math score of 28 or higher. MATH 127 or MATH 128 must be completed with a grade of C or better.

Course Syllabus: [pdf]

Grading

Component	Percentage	Date
Homework:	25%	Weekly
Participation:	10%	In Class
Midterms:	40%	10/03, 11/14
Final:	25%	12/10 13:00

Homework will be assigned weekly. There will be a "hands-on" component to the homework where students will use logic design software to build and test digital circuits.
Students may study together in groups but all assignments must be completed individually. Copying homework is unacceptable and will result in a fail in the class with an F grade.
Homework will be due at the beginning of class on the designated date. No late homeworks will be accepted unless prior notification and arrangements are made.
Students are expected to come to lecture prepared. Lecture notes will be made available online beforehand and can be printed to take notes. Additionally, lecture reading assignments should be completed before lecture in order to be successful.
Class attendance is required. You will not be successful if you are not engaged.
Class participation will be recorded through online questions using https://kahoot.it/. You will need to bring a smart phone or other web connected device (App Link) to class. Be sure to use your Webcampus (ACE) username for credit.
Exams are cumulative but will emphasize new material. All exams will be closed book and closed notes. Calculators will NOT be allowed. Questions can be answered with basic mathematics.
It is expected that you will spend 6 hours per week outside of lecture.

Gradebook

The gradebook is available through UNLV Webcampus [link].

Announcements

Date	Note
11/19/19	Updated Chapter 3 slides is posted as v1 [Ch 3 v1 pdf].
10/30/19	Office hours changed from 4-5p to 12-3:30p.
10/28/19	Class on Tu 10/29 will be canceled. Additionally, there will be no office hours on Monday or Tuesday.
09/20/19	Visit the Engineering Tutoring Lab in TBE-A 207 between 10:00-17:00 for more help with homework, labs, or studying for exams.
09/19/19	Office hours are canceled due to a faculty search presentation at 12:00. Please email if you have an urgent question.
09/10/19	First homework assignment will have grades in the gradebook today. Please be sure to check that they were recorded properly. Also, you can contact the grader, Smit Patel, either by email or in office hours for questions.
08/27/19	Welcome to Fall 2019. Please see the course introduction [pdf] Note, you should connect to the eduroam wireless network for best to have best connectivity during in-class Kahoots.

Schedule (Tentative)

Week	Date	Lecture Topic	Reading	Assignment
1	08/27 Tu	Digital Design Principles [Ch 1 pdf]	Ch 1.1-1.4	HW01 [pdf] Solutions [pdf] Due Th 09/05
1	08/29 Th	Number Systems	Ch 1.1-1.4	HW01 [pdf] Solutions [pdf] Due Th 09/05
2	09/03 Tu	Logic Gates and Truth Tables	Ch 1.5, A.1-A.2, A.7 Ch 1.6	HW02 [pdf] Solutions [pdf] Due Th 09/12
2	09/05 Th	Logic Levels	Ch 1.5, A.1-A.2, A.7 Ch 1.6	HW02 [pdf] Solutions [pdf] Due Th 09/12
3	09/10 Tu	Transistor Design	Ch 1.7-1.9 Ch 2.1-2.3.2	HW03 [pdf] Solutions [pdf] Due Th 09/19
3	09/12 Th	Boolean Equations [Ch 2 pdf]	Ch 1.7-1.9 Ch 2.1-2.3.2	HW03 [pdf] Solutions [pdf] Due Th 09/19
4	09/17 Tu	Boolean Algebra	Ch 2.3.3-2.3.5	HW04 [pdf] Solutions [pdf] Due Th 09/26
4	09/19 Th	Boolean Simplification	Ch 2.3.3-2.3.5	HW04 [pdf] Solutions [pdf] Due Th 09/26
5	09/24 Tu	Bubble Pushing	Ch 2.4-2.6
5	09/26 Th	Two-Level Logic	Ch 2.4-2.6
6	10/01 Tu	Midterm Review [mid 01 review]
6	10/03 Th	Midterm 01
7	10/08 Tu	Karnaugh Maps	Ch 2.7	HW05 [pdf] Solutions [pdf] Due Th 10/10
7	10/10 Th	K-Maps [KMap problems]	Ch 2.7	HW05 [pdf] Solutions [pdf] Due Th 10/10
8	10/15 Tu	K-Maps [KMap problems solutions]	Ch 2.8	HW06 [pdf][Hands On 1] Solutions [pdf] Due Th 10/24
8	10/17 Th	Multiplexers, Decoders	Ch 2.8	HW06 [pdf][Hands On 1] Solutions [pdf] Due Th 10/24
9	10/22 Tu	Timing: Delay and Hazards	Ch 2.9-2.10 Ch 3.1-3.2	HW07 [pdf] Solutions [pdf] Due Th 10/31
9	10/24 Th	Sequential Logic: Latches and Flip-Flops [Ch 3 pdf][Ch 3 v1 pdf]	Ch 2.9-2.10 Ch 3.1-3.2	HW07 [pdf] Solutions [pdf] Due Th 10/31
10	10/29 Tu	Registers	Ch 3.4
10	10/31 Th	Finite State Machines	Ch 3.4
11	11/05 Tu	FSM	Ch 3.4	HW08 [pdf] Solutions [pdf] Due Tu 11/12
11	11/07 Th	FSM Examples	Ch 3.4	HW08 [pdf] Solutions [pdf] Due Tu 11/12
12	11/12 Tu	Midterm Review [mid 02 review]	Ch 3.5
12	11/14 Th	Midterm 02	Ch 3.5
13	11/19 Tu	Timing Sequential Circuits	Ch 3.6	HW09 [pdf][Hands On 2] Solutions [pdf] Due Tu 11/26
13	11/21 Th	Parallelism	Ch 3.6	HW09 [pdf][Hands On 2] Solutions [pdf] Due Tu 11/26
14	11/26 Tu	Counter Designs [Ch 5 pdf]	Ch 3.6	HW10 [pdf] Solutions [pdf] Due Th 12/05
14	11/28 Th	Thanksgiving	Ch 3.6	HW10 [pdf] Solutions [pdf] Due Th 12/05
15	12/03 Tu	Final Review [final review]	Ch 5.1-5.2.3, 5.4
15	12/05 Th	Final Review	Ch 5.1-5.2.3, 5.4
16	12/10 Tu	Final	-
16	12/12 Th	-	-