Digital Logic Design I

CPE100 Fall 2018

Description

Professor:
Dr. Brendan Morris,
SEB 3216
OH: MTuWTh 16:00-17:00

Lecture: TuTh 13:00-14:15, SEB 1243
Final: Tu Dec 11, 13:00-15:00
Look up your final exam schedule now to determine conflicts.

Textbook

Digital Design and Computer Architecture, Harris and Harris, 2nd Edition, ISBN: 978-0123944245
Electronic version for reference only (not homework) [1st Ed. link]

Recommended Text

Fundamentals of Logic Design, Roth and Kinney, 7th Edition, ISBN: 978-1133628477

Catalog Description:

Logic gates. Simplification of Boolean functions. Design and testing of combinational and sequential circuits including code converters, multiplexers, adders, and synchronous counters.
Prerequisites: MATH 127 OR MATH 128 OR MATH 181 OR higher, OR SAT math score of 630 or higher OR ACT math score of 28 or higher. MATH 127 or MATH 128 must be completed with a grade of C or better.

Course Syllabus: [pdf]

Grading

Component	Percentage	Date
Homework:	25%	Weekly
Participation:	10%	In Class
Midterms:	40%	10/04, 11/15
Final:	25%	12/11 13:00

Homework will be assigned weekly. There will be a "hands-on" component to the homework where students will use logic design software to build and test digital circuits.
Students may study together in groups but all assignments must be completed individually. Copying homework is unacceptable and will result in a fail in the class with an F grade.
Homework will be due at the beginning of class on the designated date. No late homeworks will be accepted unless prior notification and arrangements are made.
Students are expected to come to lecture prepared. Lecture notes will be made available online beforehand and can be printed to take notes. Additionally, lecture reading assignments should be completed before lecture in order to be successful.
Class attendance is required. You will not be successful if you are not engaged.
Class participation will be recorded through online questions using https://kahoot.it/. You will need to bring a smart phone or other web connected device (App Link) to class. Be sure to use your Webcampus (ACE) username for credit.
Exams are cumulative but will emphasize new material. All exams will be closed book and closed notes. Calculators will NOT be allowed. Questions can be answered with basic mathematics.
It is expected that you will spend 6 hours per week outside of lecture.

Gradebook

The gradebook is available through UNLV Webcampus [link].

Announcements

Date	Note
11/14/18	You will be allowed one double-sided 8.5x11" letter sized page of handwritten notes as a cheatsheet for Midterm02.
10/09/18	Homework #5 is updated to version 2 [pdf]. This corrects a misprint on Problem 4 which made the second term look like A(BC)' instead of AB'C'. Also note that you should see slide 154 and T8' to solve Problem 1.
09/18/18	Homework 3 has been updated. The last two problems have been removed (only 8 total in new version) and will be on Homework 4.
09/13/18	Be sure to staple your homework and provide neat and clear answers for it to be graded. Additionally, you will lose 5 points if you do not answer the question of how many hours it took you to complete.
09/04/18	Homework 1 updated to have correct problem references. Also note, you should connect to the eduroam wireless network for best operation (not UNLV-Secure or UNLV-Guest). This may help with connectivity issues during in-class Kahoots.
08/27/18	Welcome to Fall 2018. Please see the course introduction [pdf]

Schedule (Tentative)

Week	Date	Lecture Topic	Reading	Assignment
1	08/28 Tu	Digital Design Principles [Ch 1 pdf]	Ch 1.1-1.4	HW01 [pdf] Solutions [pdf] Due Th 09/06
1	08/30 Th	Number Systems	Ch 1.1-1.4	HW01 [pdf] Solutions [pdf] Due Th 09/06
2	09/04 Tu	Logic Gates and Truth Tables	Ch 1.5, A.1-A.2, A.7 Ch 1.6	HW02 [pdf] Solutions [pdf] Due Th 09/13
2	09/06 Th	Logic Levels	Ch 1.5, A.1-A.2, A.7 Ch 1.6	HW02 [pdf] Solutions [pdf] Due Th 09/13
3	09/11 Tu	Transistor Design	Ch 1.7-1.9 Ch 2.1-2.3.2	HW03 [pdf] Solutions [pdf] Due Th 09/20
3	09/13 Th	Boolean Equations [Ch 2 pdf]	Ch 1.7-1.9 Ch 2.1-2.3.2	HW03 [pdf] Solutions [pdf] Due Th 09/20
4	09/18 Tu	Boolean Algebra	Ch 2.3.3-2.3.5	HW04 [pdf] Solutions [pdf] Due Th 09/27
4	09/20 Th	Boolean Simplification	Ch 2.3.3-2.3.5	HW04 [pdf] Solutions [pdf] Due Th 09/27
5	09/25 Tu	Bubble Pushing	Ch 2.4-2.6
5	09/27 Th	Two-Level Logic	Ch 2.4-2.6
6	10/02 Tu	Midterm Review [mid 01 review]
6	10/04 Th	Midterm 01
7	10/09 Tu	Karnaugh Maps	Ch 2.7	HW05 [pdf] Solutions [pdf] Due Th 10/11
7	10/11 Th	K-Maps	Ch 2.7	HW05 [pdf] Solutions [pdf] Due Th 10/11
8	10/16 Tu	K-Maps [KMap problems]	Ch 2.8	HW06 [pdf][Hands On 1] Solutions [pdf] Due Th 10/25
8	10/18 Th	Multiplexers, Decoders	Ch 2.8	HW06 [pdf][Hands On 1] Solutions [pdf] Due Th 10/25
9	10/23 Tu	Timing: Delay and Hazards	Ch 2.9-2.10 Ch 3.1-3.2	HW07 [pdf] Solutions [pdf] Due Th 11/01
9	10/25 Th	Sequential Logic: Latches and Flip-Flops [Ch 3 pdf]	Ch 2.9-2.10 Ch 3.1-3.2	HW07 [pdf] Solutions [pdf] Due Th 11/01
10	10/30 Tu	Registers	Ch 3.4
10	11/01 Th	Finite State Machines	Ch 3.4
11	11/06 Tu	FSM	Ch 3.4	HW08 [pdf] Solutions [pdf] Due Tu 11/13
11	11/08 Th	FSM Examples	Ch 3.4	HW08 [pdf] Solutions [pdf] Due Tu 11/13
12	11/13 Tu	Midterm Review [mid 02 review]	Ch 3.5
12	11/15 Th	Midterm 02	Ch 3.5
13	11/20 Tu	Timing Sequential Circuits		HW09 [pdf][Hands On 2] Solutions [pdf] Due Th 11/29
13	11/22 Th	Thanksgiving		HW09 [pdf][Hands On 2] Solutions [pdf] Due Th 11/29
14	11/27 Tu	Parallelism	Ch 3.6	HW10 [pdf] Solutions [pdf] Due Th 12/06
14	11/29 Th	Counter Designs [Ch 5 pdf]	Ch 3.6	HW10 [pdf] Solutions [pdf] Due Th 12/06
15	12/04 Tu	Final Review [final review]	Ch 5.1-5.2.3, 5.4
15	12/06 Th	Final Review	Ch 5.1-5.2.3, 5.4
16	12/11 Tu	Final	-
16	12/13 Th	-	-