Digital Logic Design I

CPE100 - 1002 Fall 2023


Description

Professor:
Dr. Brendan Morris,
SEB 3216
OH: TuTh 13:30-14:30

Lecture: TuTh 16:00-17:15, SEB 1242
Final: Tu Dec 12, 18:00-20:00
Look up your final exam schedule now to determine conflicts.

Tutoring:
Engineering Tutoring Lab, TBE-A 309

You are highly encouraged to take advantage of the tutoring services. 1) You are paying for them and 2) students find the services helpful since the tutors have recently finished the course and are quite knowledgeable.

Textbook

Digital Design and Computer Architecture, Harris and Harris, 2nd Edition, ISBN: 978-0123944245 [direct link] [library link]

Be sure to either use the UNLV VPN, go through the UNLV library access using your ACE account, or through the AccessEngineering Library login.

Recommended Text

Fundamentals of Logic Design, Roth and Kinney, 7th Edition, ISBN: 978-1133628477

Catalog Description:

Logic gates. Simplification of Boolean functions. Design and testing of combinational and sequential circuits including code converters, multiplexers, adders, and synchronous counters.
Prerequisites: MATH 127 OR MATH 128 OR MATH 181 OR higher, OR SAT math score of 630 or higher OR ACT math score of 28 or higher. MATH 127 or MATH 128 must be completed with a grade of C or better.

Course Syllabus: [pdf]

Grading

ComponentPercentageDate
Homework: 25% Weekly
Participation: 10% "In Class"
Midterms: 40% 10/05, 11/21
Final: 25% 12/12

Gradebook

The gradebook is available through UNLV Webcampus [link].

Virtual Resources

This section will be updated with useful items during the course. Please email anything you think is useful for the class.

Schedule (Tentative)

Course content will be posted in the Schedule below. Lecture (Panopto) and Discussion (Zoom) can be found on Webcampus.

WeekDateLecture Topic/RecordingReadingAssignment
1 08/29 Tu class01: Intro [pdf] [Zoom]
Digital Design Principles [vid]
[Ch1 slides]
Ch1.1-1.3
Ch1.4
HW01 [pdf]
Due Su 09/10
Solutions [pdf]
08/31 Th class02: Number Systems [vid1-representations][vid2-addition] [Zoom]
2 09/05 Tu class03: Logic Gates + Truth Tables [vid] [Zoom] Ch1.5-1.6
A.1-A.2, A.6
HW02 [pdf]
Due Su 09/17
Solutions [pdf]
09/07 Th class04: Logic Levels [vid] [Zoom]
3 09/12 Tu class05: Transistors [vid1] + Power [vid2] [Zoom] Ch1.7-1.9
Ch 2.1-2.3.2
HW03 [pdf][comp0]
Due Su 09/24
Solutions [pdf]
09/14 Th class06: Boolean Intro [vid1] + Equations [vid2] [Zoom]
4 09/19 Tu class07: Boolean Algebra [vid1-axioms/theorems][vid2-multivar theorems] [Zoom] [Ch2 slides]
Ch 2.3.3-2.3.5
HW04 [pdf]
Due Su 10/01
Solutions [pdf]
09/21 Th class08: Boolean Simplification [vid] [Zoom]
5 09/26 Tu class09: Two-Level Logic [vid] Ch 2.4-2.6
09/28 Th class10: Bubble Pushing [Zoom]
6 10/03 Tu class11: Midterm Review [Zoom]
10/05 Th class12: Midterm01
7 10/10 Tu class13: Karnaugh Maps [vid] [Zoom] Ch 2.7 HW05 [pdf]
Due Su 10/23
Solutions [pdf]
10/12 Th class14: K-Maps [KMap problems] [Zoom]
8 10/17 Tu class15: K-Maps [KMap problems solutions] [Zoom] Ch 2.8 HW06 [pdf][comp1]
Due Su 10/29
Solutions [pdf]
10/19 Th class16: Multiplexers, Decoders [vid] [Zoom]
9 10/24 Tu class17: Timing: Delay and Hazards [vid] [WebEx] Ch 2.9-2.10
Ch 3.1-3.2
HW07 [pdf][comp2]
Due Su 11/05
Solutions [pdf]
10/26 Th class18: Sequential Logic: Latches and Flip-Flops [vid] [WebEx]
10 10/31 Tu class19: Registers [Zoom] [Ch3 slides]
Ch 3.4
11/02 Th class20: Finite State Machines [vid] [Zoom]
11 11/07 Tu class21: FSM [Zoom] Ch 3.4 HW08 [pdf]
Due Su 11/13
Solutions [pdf]
11/09 Th class22: FSM Examples [Zoom]
12 11/14 Tu class23: Midterm Review [Zoom] Ch 3.5.1-3.5.2
11/16 Th class24: Timing Sequential Circuits [vid][Zoom]
13 11/21 Tu class25: Midterm02 Ch 3.6 HW09 [pdf][comp3]
Solutions [pdf]
Due Su 11/26
11/23 Th class26: Thanksgiving
14 11/29 Tu class27: Parallelism [vid][Zoom] [Ch 5 pdf]
Ch 5.1-5.2.3, 5.4
HW10 [pdf]
Solutions [pdf]
Due Su 12/04
12/01 Th class28: Adder Design [Zoom]
15 12/05 Tu class29: Building Blocks [vid][Zoom] Ch 1-3, 5
12/07 Th class30: Final Review [Zoom]
16 12/12 Tu Final
-
12/14 Th -