Digital Logic Design I

CPE100 Fall 2018


Description

Professor:
Dr. Brendan Morris,
SEB 3216
OH: MTuWTh 16:00-17:00

Lecture: TuTh 13:00-14:15, SEB 1243
Final: Tu Dec 11, 13:00-15:00
Look up your final exam schedule now to determine conflicts.

Textbook

Digital Design and Computer Architecture, Harris and Harris, 2nd Edition, ISBN: 978-0123944245
    Electronic version for reference only (not homework) [1st Ed. link]

Recommended Text

Fundamentals of Logic Design, Roth and Kinney, 7th Edition, ISBN: 978-1133628477

Catalog Description:

Logic gates. Simplification of Boolean functions. Design and testing of combinational and sequential circuits including code converters, multiplexers, adders, and synchronous counters.
Prerequisites: MATH 127 OR MATH 128 OR MATH 181 OR higher, OR SAT math score of 630 or higher OR ACT math score of 28 or higher. MATH 127 or MATH 128 must be completed with a grade of C or better.

Course Syllabus: [pdf]

Grading

ComponentPercentageDate
Homework: 25% Weekly
Participation: 10% In Class
Midterms: 40% 10/04, 11/15
Final: 25% 12/11 13:00

Gradebook

The gradebook is available through UNLV Webcampus [link].

Announcements

DateNote
11/14/18 You will be allowed one double-sided 8.5x11" letter sized page of handwritten notes as a cheatsheet for Midterm02.
10/09/18 Homework #5 is updated to version 2 [pdf]. This corrects a misprint on Problem 4 which made the second term look like A(BC)' instead of AB'C'. Also note that you should see slide 154 and T8' to solve Problem 1.
09/18/18 Homework 3 has been updated. The last two problems have been removed (only 8 total in new version) and will be on Homework 4.
09/13/18 Be sure to staple your homework and provide neat and clear answers for it to be graded. Additionally, you will lose 5 points if you do not answer the question of how many hours it took you to complete.
09/04/18 Homework 1 updated to have correct problem references.
Also note, you should connect to the eduroam wireless network for best operation (not UNLV-Secure or UNLV-Guest). This may help with connectivity issues during in-class Kahoots.
08/27/18 Welcome to Fall 2018. Please see the course introduction [pdf]

Schedule (Tentative)

WeekDateLecture TopicReadingAssignment
1 08/28 Tu Digital Design Principles [Ch 1 pdf] Ch 1.1-1.4 HW01 [pdf]
Solutions [pdf]
Due Th 09/06
08/30 Th Number Systems
2 09/04 Tu Logic Gates and Truth Tables Ch 1.5, A.1-A.2, A.7
Ch 1.6
HW02 [pdf]
Solutions [pdf]
Due Th 09/13
09/06 Th Logic Levels
3 09/11 Tu Transistor Design Ch 1.7-1.9
Ch 2.1-2.3.2
HW03 [pdf]
Solutions [pdf]
Due Th 09/20
09/13 Th Boolean Equations [Ch 2 pdf]
4 09/18 Tu Boolean Algebra Ch 2.3.3-2.3.5 HW04 [pdf]
Solutions [pdf]
Due Th 09/27
09/20 Th Boolean Simplification
5 09/25 Tu Bubble Pushing Ch 2.4-2.6
09/27 Th Two-Level Logic
6 10/02 Tu Midterm Review [mid 01 review]
10/04 Th Midterm 01
7 10/09 Tu Karnaugh Maps Ch 2.7 HW05 [pdf]
Solutions [pdf]
Due Th 10/11
10/11 Th K-Maps
8 10/16 Tu K-Maps [KMap problems] Ch 2.8 HW06 [pdf][Hands On 1]
Solutions [pdf]
Due Th 10/25
10/18 Th Multiplexers, Decoders
9 10/23 Tu Timing: Delay and Hazards Ch 2.9-2.10
Ch 3.1-3.2
HW07 [pdf]
Solutions [pdf]
Due Th 11/01
10/25 Th Sequential Logic: Latches and Flip-Flops [Ch 3 pdf]
10 10/30 Tu Registers
Ch 3.4
11/01 Th Finite State Machines
11 11/06 Tu FSM Ch 3.4 HW08 [pdf]
Solutions [pdf]
Due Tu 11/13
11/08 Th FSM Examples
12 11/13 Tu Midterm Review [mid 02 review] Ch 3.5
11/15 Th Midterm 02
13 11/20 Tu Timing Sequential Circuits HW09
Due Th 11/29
11/22 Th Thanksgiving
14 11/27 Tu Parallelism Ch 3.6 HW10
Due Th 12/06
11/29 Th Counter Designs [Ch 5 pdf]
15 12/04 Tu Quine-McCluskey Ch 5.4.1
12/06 Th Final Review
16 12/11 Tu Final
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12/13 Th -