Digital Logic Design I

CPE100 Fall 2017


Dr. Brendan Morris,
SEB 3216
OH: MTuWTh 16:00-17:00

Lecture: TuTh 13:00-14:15, SEB 1243
Final: Tu Dec 12, 13:00-15:00
Look up your final exam schedule now to determine conflicts.


Digital Design and Computer Architecture, Harris and Harris, 2nd Edition, ISBN: 978-0123944245; For reference only (not homework) [1st Ed. link]

Recommended Text

Fundamentals of Logic Design, Roth and Kinney, 7th Edition, ISBN: 978-1133628477

Catalog Description:

Logic gates. Simplification of Boolean functions. Design and testing of combinational and sequential circuits including code converters, multiplexers, adders, and synchronous counters.
Prerequisites: MATH 127 OR MATH 128 OR MATH 181 OR higher, OR SAT math score of 630 or higher OR ACT math score of 28 or higher. MATH 127 or MATH 128 must be completed with a grade of C or better.

Course Syllabus: [pdf]


Midterms: 40% TBD: 10/05, 11/14
Final: 30% 12/14 15:10
Homework: 30%

Students will use logic design software to build and test digital circuits as part of homework assignments. Students may study together in groups but all assignments must be completed individually. Homework will be due in class on the designated date. No late homeworks will be accepted unless prior notification and arrangements are made.


The gradebook is available through UNLV Webcampus [link].


11/29/17 Hands On Assignment #2 due date is Th 12/07 not 11/30.
11/20/17 No homework is due Tu 11/21. Next homework is Th 11/30.
11/08/17 Note: updated schedule. HW08 now due Tu 11/14 and Midterm02 is Th 11/16.
10/11/17 Updated HW05 is available.
10/03/17 HW03 solutions reposted to reflect correct number of total points. HW04 solutions reposted to reflect errors in Problem 1 and Problem 5(d)
09/16/17 Note: homework will now be due at the beginning of class, otherwise it will not be accepted. In addition, you will not get points if your assignment is not stapled together or is messy or unreadable.
09/14/17 In order to make it more clear what is happening in each lecture, the lecture notes will now be posted in pieces.
09/06/17 Get involved with student organizations on campus. Find fun things to do, expand your network, and get more out of school. See the linked document for listing of UNLV student organizations in Engineering, contact information, and meeting times [pdf].
09/04/17 Full lecture notes for Chapter 1 (v1) are now available [Ch 1 pdf (v1)].
08/30/17 The first homework is now posted online as well as lecture notes. This first release (v0) is not for the entire Chapter 1 yet. I suggest you print these for lecture using 4 pages a sheet in landscape mode.
08/28/17 Welcome to Fall 2017.

Schedule (Tentative)

WeekDateLecture TopicReadingAssignment
1 08/29 Tu Digital Design Principles [pdf] Ch 1.1-1.4 HW01 [pdf]
Solutions [pdf]
Due Th 09/07
08/31 Th Number Systems [Ch 1 pdf (v0)]
2 09/05 Tu Logic Gates and Truth Tables [Ch 1 pdf (v1)] Ch 1.5, A.1-A.2, A.7
Ch 1.6
HW02 [pdf]
Solutions [pdf]
Due Th 09/14
09/07 Th Logic Levels
3 09/12 Tu Transistor Design Ch 1.7-1.9
Ch 2.1-2.3.2
HW03 [pdf]
Solutions [pdf]
Due Th 09/21
09/14 Th Boolean Equations [Ch 2 lec0000]
4 09/19 Tu Boolean Algebra [Ch 2 lec0001] Ch 2.3.3-2.3.5 HW04 [pdf]
Solutions [pdf]
Due Th 09/28
09/21 Th Boolean Simplification [Ch 2 lec0010]
5 09/26 Tu Bubble Pushing [Ch 2 lec0011] Ch 2.4-2.6
09/28 Th Two-Level Logic
6 10/03 Tu Midterm Review [mid 01 review] HW05 [pdf]
Solutions [pdf]
Due Th 10/12
10/05 Th Midterm 01
7 10/10 Tu Karnaugh Maps [Ch 2 lec0100] Ch 2.7 HW06
Due Th 10/19
10/12 Th K-Maps [Ch 2 lec0101]
8 10/17 Tu Quine-McCluskey Method Ch 2.8 HW06 [pdf][Hands On][PIN .qsf]
Solutions [pdf]
Due Th 10/26
10/19 Th Multiplexers, Decoders
9 10/24 Tu Timing: Delay and Hazards [Ch 2 lec0110] Ch 2.9-2.10
Ch 3.1-3.2
HW07 [pdf]
Solutions [pdf]
Due Th 11/02
10/26 Th Sequential Logic: Latches and Flip-Flops [Ch 3 Seq Elements]
10 10/31 Tu Registers
Ch 3.4
11/02 Th Finite State Machines [Ch 3 FSM]
11 11/07 Tu FSM Ch 3.4 HW08 [pdf]
Solutions [pdf]
Due Tu 11/14
11/09 Th FSM Examples [Ch 3 FSM_v2]
12 11/14 Tu Midterm Review [mid 02 review] Ch 3.5
11/16 Th Midterm 02
13 11/21 Tu Timing Sequential Circuits [Ch 3 Timing] HW09 [pdf][Hands On]
Solutions [pdf]
Due Th 11/30
11/23 Th Thanksgiving
14 11/28 Tu Parallelism [Ch 3 Parallelism] Ch 3.6 HW10 [pdf]
Solutions [pdf]
Due Th 12/07
11/30 Th Counter Designs [Ch 5 building blocks]
15 12/05 Tu Quine-McCluskey [pdf] Ch 5.4.1
12/07 Th Final Review [final review v2]
16 12/12 Tu Final
12/14 Th -